? semiconductor components industries, llc, 2001 september, 2001 rev. 2 1 publication order number: ntd3055l104/d ntd3055l104 power mosfet 12 amps, 60 volts, logic level nchannel dpak designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. features ? lower r ds(on) ? lower v ds(on) ? tighter v sd specification ? lower diode reverse recovery time ? lower reverse recovery stored charge typical applications ? power supplies ? converters ? power motor controls ? bridge circuits maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 60 vdc draintogate voltage (r gs = 10 m w ) v dgr 60 vdc gatetosource voltage continuous nonrepetitive (t p 10 ms) v gs v gs 15 20 vdc drain current continuous @ t a = 25 c continuous @ t a = 100 c single pulse (t p 10 m s) i d i d i dm 12 10 45 adc apk total power dissipation @ t a = 25 c derate above 25 c total power dissipation @ t a = 25 c (note 1) total power dissipation @ t a = 25 c (note 2) p d 48 0.32 2.1 1.5 w w/ c w w operating and storage temperature range t j , t stg 55 to +175 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 vdc, v gs = 5.0 vdc, l = 1.0 mh i l(pk) = 11 a, v ds = 60 vdc) e as 61 mj thermal resistance junctiontocase junctiontoambient (note 1) junctiontoambient (note 2) r q jc r q ja r q ja 3.13 71.4 100 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using 1 pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using the minimum recommended pad size, (cu area 0.412 in 2 ). 12 amperes 60 volts r ds(on) = 104 m w device package shipping ordering information ntd3055l104 dpak 75 units/rail case 369a dpak (bent lead) style 2 marking diagrams & pin assignments http://onsemi.com nchannel d s g ntd3055l104 = device code y = year ww = work week yww ntd 3055l104 1 2 3 4 1 gate 3 source 2 drain 4 drain ntd3055l1041 dpak straight lead 75 units/rail ntd3055l104t4 dpak 2500/tape & reel case 369 dpak (straight lead) style 2 yww ntd 3055l104 1 gate 3 source 2 drain 4 drain 1 2 3 4
ntd3055l104 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (note 3) (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 60 70 62.9 vdc mv/ c zero gate voltage drain current (v ds = 60 vdc, v gs = 0 vdc) (v ds = 60 vdc, v gs = 0 vdc, t j = 150 c) i dss 1.0 10 m adc gatebody leakage current (v gs = 15 vdc, v ds = 0 vdc) i gss 100 nadc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 1.0 1.6 4.2 2.0 vdc mv/ c static draintosource onresistance (note 3) (v gs = 5.0 vdc, i d = 6.0 adc) r ds(on) 89 104 mohm static draintosource onvoltage (note 3) (v gs = 5.0 vdc, i d = 12 adc) (v gs = 5.0 vdc, i d = 6.0 adc, t j = 150 c) v ds(on) 0.98 0.86 1.50 vdc forward transconductance (note 3) (v ds = 8.0 vdc, i d = 6.0 adc) g fs 9.1 mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss 316 440 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss 105 150 transfer capacitance f = 1 . 0 mhz) c rss 35 70 switching characteristics (note 4) turnon delay time t d(on) 9.2 20 ns rise time (v dd = 30 vdc, i d = 12 adc, t r 104 210 turnoff delay time (v dd 30 vdc , i d 12 adc , v gs = 5.0 vdc, r g = 9.1 w ) (note 3) t d(off) 19 40 fall time t f 40.5 80 gate charge (v 48 vd i 12 ad q t 7.4 20 nc (v ds = 48 vdc, i d = 12 adc, v gs = 5.0 vdc ) ( note 3 ) q 1 2.0 v gs = 5 . 0 vdc) (note 3) q 2 4.0 sourcedrain diode characteristics forward onvoltage (i s = 12 adc, v gs = 0 vdc) (note 3) (i s = 12 adc, v gs = 0 vdc, t j = 150 c) v sd 0.95 0.82 1.2 vdc reverse recovery time (i 12 ad v 0vd t rr 35 ns (i s = 12 adc, v gs = 0 vdc, di s /dt = 100 a/ m s ) ( note 3 ) t a 21 di s /dt = 100 a/ m s) (note 3) t b 14 reverse recovery stored charge q rr 0.04 m c 3. pulse test: pulse width 300 m s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd3055l104 http://onsemi.com 3 0 0.12 16 12 0.08 0.04 0 820 0.32 24 1.6 1.2 1.4 1 0.8 0.6 1 100 10,000 08 8 2 1 v ds , draintosource voltage (volts) i d , drain current (amps) 0 v gs , gatetosource voltage (volts) figure 1. onregion characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.16 8 0.08 0 412 figure 3. onresistance versus gatetosource voltage i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage i d , drain current (amps) r ds(on) , draintosource resistance ( w ) r ds(on) , draintosource resistance ( w ) figure 5. onresistance variation with temperature t j , junction temperature ( c) figure 6. draintosource leakage current versus voltage v ds , draintosource voltage (volts) r ds(on) , draintosource resistance (normalized) i dss , leakage (na) 24 50 50 25 0 25 75 125 100 1 2.5 6 040 30 20 60 10 3 4 12 8 v v ds 10 v t j = 25 c t j = 55 c t j = 100 c t j = 100 c v gs = 5 v v gs = 10 v 150 175 v gs = 0 v i d = 6 a v gs = 5 v 16 0.32 v gs = 10 v t j = 25 c t j = 55 c t j = 100 c 24 t j = 150 c t j = 100 c 0 24 8 16 3.5 4 t j = 25 c t j = 55 c 50 10 6 v 4.5 v 4 v 3 v 1.8 4 5 6 7 1.5 2 3 4.5 5 5.5 0.24 16 20 0.24 0.28 2 20 5 v 3.5 v 4 0.20 0.16 1000 20 4 12 0.12 0.04 0.28 0.20
ntd3055l104 http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. c rss 10 0 10 15 20 25 gatetosource or draintosource voltage (volts) c, capacitance (pf) figure 7. capacitance variation 1000 200 0 v gs v ds 400 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 600 800
ntd3055l104 http://onsemi.com 5 16 0 0.3 draintosource diode characteristics v sd , sourcetodrain voltage (volts) figure 8. gatetosource and draintosource voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v figure 10. diode forward voltage versus current v gs , gatetosource voltage (volts) 0 5 3 1 0 q g , total gate charge (nc) 6 4 2 4 100 28 0.5 1 2 4 6 i d = 12 a t j = 25 c v gs q 2 q 1 q t t r t d(off) t d(on) t f 10 v ds = 30 v i d = 12 a v gs = 5 v 0.7 0.9 6 8 0.8 0.6 0.4 10 12 14 t j = 150 c t j = 25 c safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
ntd3055l104 http://onsemi.com 6 safe operating area figure 11. maximum rated forward biased safe operating area t j , starting junction temperature ( c) e as , single pulse draintosource figure 12. maximum avalanche energy versus starting junction temperature 0.1 1 100 v ds , draintosource voltage (volts) figure 13. thermal response 1 100 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 0 25 50 75 100 125 10 i d = 11 a 10 10 175 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 30 70 v gs = 15 v single pulse t c = 25 c 1 ms 100 m s 10 ms dc 10 m s 150 50 r(t), effective transient thermal resistance (normalized) t, time ( m s) 0.1 1.0 0.01 110 0.1 0.01 0.001 0.0001 0.00001 20 40 50 60 0.2 d = 0.5 0.1 r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.05 0.01 single pulse 0.02
ntd3055l104 http://onsemi.com 7 package dimensions style 2: pin 1. gate 2. drain 3. source 4. drain d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h t seating plane z dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.175 0.215 4.45 5.46 s 0.020 0.050 0.51 1.27 u 0.020 --- 0.51 --- v 0.030 0.050 0.77 1.27 z 0.138 --- 3.51 --- notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 dpak case 369a13 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k t seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.250 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.033 0.040 0.84 1.01 f 0.037 0.047 0.94 1.19 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.175 0.215 4.45 5.46 s 0.050 0.090 1.27 2.28 v 0.030 0.050 0.77 1.27 dpak case 36907 issue m
ntd3055l104 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ntd3055l104/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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